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this data sheet contains design specifications for product development. ramtron international corporation these specifications may change in any manner without not ice 1850 ramtron drive, colorado springs, co 80921 (800) 545 - fram, (719) 481 - 7000, fax (719) 481 - 7058 www.ramtron.com 28 july 2000 1 / 13 FM24C04 4kb fram serial memory features 4k bit ferroelectric nonvolatile ram organized as 512 x 8 bits high endurance 10 billion (10 10 ) read/writes 10 year data retention at 85 c no write delay advanced high - reliability ferroe lectric process fast two - wire serial interface up to 400 khz maximum bus frequency direct hardware replacement for eeprom low power operation true 5v operation 150 m a active current (100 khz) 10 m a standby current industry standard configuration ind ustrial temperature - 40 c to +85 c 8 - pin sop or dip description the FM24C04 is a 4 - kilobit nonvolatile memory employing an advanced ferroelectric process. a ferroelectric random access memory, or fram, is nonvolatile but operates in other respects as a ram. it provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by eeprom and other nonvolatile memories. unlike serial eeproms, the FM24C04 performs write operations at bus speed. no write delays are incurred. data is written to the memory array mere hundreds of nanoseconds after it has been successfully transferred to the device. the next bus cycle may commence immediately. in addition the product offers substantial write e ndurance compared with other nonvolatile memories. the FM24C04 is capable of supporting up to 1e10 read/write cycles -- far more than most systems will require from a serial memory. these capabilities make the FM24C04 ideal for nonvolatile memory applic ations requiring frequent or rapid writes. examples range from data collection where the number of write cycles may be critical, to demanding industrial controls where the long write time of eeprom can cause data loss. the combination of features allows m ore frequent data writing with less overhead for the system. the FM24C04 provides substantial benefits to users of serial eeprom, yet these benefits are available in a hardware drop - in replacement. the FM24C04 is provided in industry standard 8 - pin packa ges using a familiar two - wire protocol. they are guaranteed over an industrial temperature range of - 40c to +85c. pin configuration pin names function a1 device select address 1 a2 device select address 2 sda serial data/address s cl serial clock wp write protect vss ground vdd supply voltage 5v ordering information FM24C04 - p 8 - pin plastic dip FM24C04 - s 8 - pin sop nc a1 a2 vss vdd wp scl sda
ramtron FM24C04 28 july 2000 2 / 13 figure 1. block diagram address latch ` 64 x 64 fram array data latch 8 sda counter serial to parallel converter control logic scl wp pin description pin name pin number i/o pin descrip tion nc 1 no connect. a1 - a2 2 - 3 i address 1, 2. the address pins set the device address. the device address value in the 2 - wire slave address must match the setting of these two pins. vss 4 i ground sda 5 i/o serial data address. this is a bi - direct ional data line for the two - wire interface. it is open - drain and is intended to be wire - ored with other devices on the two - wire bus. the input buffer incorporates a schmitt trigger for noise immunity and the output driver includes slope control for falling edges. scl 6 i serial clock. the serial clock line for the two - wire interface. data is clocked out of the part on the falling edge and in on the rising edge. wp 7 i write protect. when tied to vdd, addresses in the upper half of the logical memory map ( a0=1 in the slave address) will be write - protected. write access to the lower half of the addresses is permitted. when wp is connected to ground, all addresses may be written. this pin must not be left floating. vdd 8 i supply voltage. 5v
ramtron FM24C04 28 july 2000 3 / 13 overview th e FM24C04 is a serial fram memory. the memory array is logically organized as 512 x 8 and is accessed using an industry standard two - wire interface. functional operation of the fram is similar to serial eeproms. the major difference between the FM24C04 and a serial eeprom with the same pin - out relates to its superior write performance. memory architecture when accessing the FM24C04, the user addresses 512 locations each with 8 data bits. these data bits are shifted serially. the 512 addresses are accessed using the two - wire protocol, which includes a slave address (to distinguish other devices), a page address, and a word address. the word address consists of 8 - bits that specify one of 256 addresses. the page address is 1 - bit and so there are 2 pages each o f 256 locations. the complete address of 9 - bits specifies each byte address uniquely. most functions of the FM24C04 either are controlled by the two - wire interface or are handled automatically by on - board circuitry. the access time for memory operation e ssentially is zero, beyond the time needed for the serial protocol. that is, the memory is read or written at the speed of the two - wire bus. unlike an eeprom, it is not necessary to poll the device for a ready condition since writes occur at bus speed. tha t is, by the time a new bus transaction can be shifted into the part, a write operation will be complete. this is explained in more detail in the interface section below. users expect several obvious system benefits from the FM24C04 due to its fast write cycle and high endurance as compared with eeprom. however there are less obvious benefits as well. for example in a high noise environment, the fast - write operation is less susceptible to corruption than an eeprom since it is completed quickly. by contras t an eeprom requiring milliseconds to write is vulnerable to noise during much of the cycle. note that the FM24C04 contains no power management circuits other than a simple internal power - on reset. it is the user?s responsibility to ensure that vdd is wi thin data sheet tolerances to prevent incorrect operation. two - wire interface the FM24C04 employs a bi - directional two - wire bus protocol using few pins and little board space. figure 2 illustrates a typical system configuration using the FM24C04 in a mic rocontroller - based system. the industry standard two - wire bus is familiar to many users but is described in this section. by convention, any device that is sending data onto the bus is the transmitter while the target device for this data is the receiver . the device that is controlling the bus is the master. the master is responsible for generating the clock signal for all operations. any device on the bus that is being controlled is a slave. the FM24C04 is always a slave device. the bus protocol is con trolled by transition states in the sda and scl signals. there are four conditions including start, stop, data bit, or acknowledge. figure 3 illustrates the signal conditions that specify the four states. detailed timing diagrams are in the electrical spec ifications. figure 2. typical system configuration microcontroller sda scl FM24C04 a1 a2 sda scl fm24c64 a0 a1 a2 vdd rmin = 1.8 k w rmax = tr/cbus
ramtron FM24C04 28 july 2000 4 / 13 figure 3. data transfer protocol start condition a start condition is indicated when the bus master drives sda from high to low while the scl signal is high. all command s must be preceded by a start condition. an operation in progress can be aborted by asserting a start condition at any time. aborting an operation using the start condition will ready the FM24C04 for a new operation. if during operation the power supply drops below the specified vdd minimum, the system should issue a start condition prior to performing another operation. stop condition a stop condition is indicated when the bus master drives sda from low to high while the scl signal is high. all operatio ns using the FM24C04 should end with a stop condition. if an operation is in progress when a stop is asserted, the operation will be aborted. the master must have control of sda (not a memory read) in order to assert a stop condition. data/address transfe r all data transfers (including addresses) take place while the scl signal is high. except under the two conditions described above, the sda signal should not change while scl is high. acknowledge the acknowledge takes place after the 8 th data bit has bee n transferred in any transaction. during this state the transmitter should release the sda bus to allow the receiver to drive it. the receiver drives the sda signal low to acknowledge receipt of the byte. if the receiver does not drive sda low, the conditi on is a no - acknowledge and the operation is aborted. the receiver would fail to acknowledge for two distinct reasons. first is that a byte transfer fails. in this case the no - acknowledge ceases the current operation so that the part can be addressed again . this allows the last byte to be recovered in the event of a communication error. second and most common, the receiver does not acknowledge to deliberately end an operation. for example, during a read operation, the FM24C04 will continue to place data o nto the bus as long as the receiver sends acknowledges (and clocks). when a read operation is complete and no more data is needed, the receiver must not acknowledge the last byte. if the receiver acknowledges the last byte, this will cause the FM24C04 to attempt to drive the bus on the next clock while the master is sending a new command such as stop. slave address the first byte that the FM24C04 expects after a start condition is the slave address. as shown in figure 4, the slave address contains the dev ice type, the device select, the page of memory to be accessed, and a bit that specifies if the transaction is a read or a write. bits 7 - 4 are the device type and should be set to 1010b for the FM24C04. the device type allows other types of functions to reside on the 2 - wire bus within an identical address range. bits 3 - 2 are the device address. if bit 3 matches the a2 pin and bit 2 matches the a1 pin the device will be selected. bit 1 is the page select. it specifies the 256 - byte block of memory that is t argeted for the current operation. bit 0 is the read/write bit. a 0 indicates a write operation. word address after the FM24C04 (as receiver) acknowledges the slave id, the master will place the word address on the bus for a write operation. the word add ress is the lower 8 - bits of the address to be combined with the 1 - bit page select to specify exactly the byte to be written. the complete 9 - bit address is latched internally.
ramtron FM24C04 28 july 2000 5 / 13 figure 4. slave address no word address occurs for a read ope ration. reads always use the lower 8 - bits that are held internally in the address latch and the 9 th address bit is part of the slave address. reads always begin at the address following the previous access. a random read address can be loaded by doing a wr ite operation as explained below. after transmission of each data byte, just prior to the acknowledge, the FM24C04 increments the internal address latch. this allows the next sequential byte to be accessed with no additional addressing. after the last ad dress (1ffh) is reached, the address latch will roll over to 000h. there is no limit to the number of bytes that can be accessed with a single read or write operation. data transfer after all address information has been transmitted, data transfer between the bus master and the FM24C04 can begin. for a read operation the FM24C04 will place 8 data bits on the bus then wait for an acknowledge. if the acknowledge occurs, the next sequential byte will be transferred. if the acknowledge is not sent, the read op eration is concluded. for a write operation, the FM24C04 will accept 8 data bits from the master then send an acknowledge. all data transfer occurs msb (most significant bit) first. memory operation the FM24C04 is designed to operate in a manner very sim ilar to other 2 - wire interface memory products. the major differences result from the higher performance write capability of fram technology. these improvements result in some differences between the FM24C04 and a similar configuration eeprom during writes . the complete operation for both writes and reads is explained below. write operation all writes begin with a slave address then a word address as mentioned above. the bus master indicates a write operation by setting the lsb of the slave address to a 0. after addressing, the bus master sends each byte of data to the memory and the memory generates an acknowledge condition. any number of sequential bytes may be written. if the end of the address range is reached internally, the address counter will wrap f rom 1ffh to 000h. unlike other nonvolatile memory technologies, there is no effective write delay with fram. since the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. the entire memory cyc le occurs in less time than a single bus clock. therefore any operation including read or write can occur immediately following a write. acknowledge polling, a technique used with eeproms to determine if a write is complete is unnecessary and will always r eturn a done condition. an actual memory array write occurs after the 8 th data bit is transferred. it will be complete before the acknowledge is sent. therefore if the user desires to abort a write without altering the memory contents, this should be don e using a start or stop condition prior to the 8 th data bit. the FM24C04 needs no page buffering. portions of the memory array can be write protected using the wp pin. setting the wp pin to a high condition (vdd) will write - protect addresses from 100h to 1ffh. the FM24C04 will not acknowledge data bytes that are written to protected addresses. in addition, the address counter will not increment if writes are attempted to these addresses. setting wp to a low state (vss) will deactivate this feature. wp mus t not be left floating. figure 5 below illustrates both a single - byte and multiple - write.
ramtron FM24C04 28 july 2000 6 / 13 figure 5 byte write figure 6 multiple byte write s s l a v e a d d r e s s 0 b y m a s t e r b y f m 2 4 c 0 4 s t a r t a d d r e s s a n d d a t a s t o p a a c k n o w l e d g e w o r d a d d r e s s a d a t a b y t e a p d a t a b y t e a a read operation there are two basic types of read operations. they are cur rent address read and selective address read. in a current address read, the FM24C04 uses the internal address latch to supply the lower 8 address bits. in a selective read, the user performs a procedure to set these lower address bits to a specific value . current address & sequential read as mentioned above the FM24C04 uses an internal latch to supply the lower 8 address bits for a read operation. a current address read uses the existing value in the address latch as a starting place for the read operat ion. this is the address immediately following that of the last operation. to perform a current address read, the bus master supplies a slave address with the lsb set to 1. this indicates that a read operation is requested. the page select bit in the sla ve address specifies the block of memory that is used for the read operation. after the acknowledge, the FM24C04 will begin shifting out data from the current address. the current address is the bit from the slave address combined with the 8 bits that were in the internal address latch. beginning with the current address, the bus master can read any number of bytes. thus a sequential read is simply a current address read with multiple byte transfers. after each byte the internal address counter will be in cremented. each time the bus master acknowledges a byte, this indicates that the FM24C04 should read out the next sequential byte. there are four ways to properly terminate a read operation. failing to properly terminate the read will most likely create a bus contention as the FM24C04 attempts to read out additional data onto the bus. the four valid methods are as follows. 1. the bus master issues a no - acknowledge in the 9 th clock cycle and a stop in the 10 th clock cycle. this is illustrated in the diagrams below. this is the preferred method. 2. the bus master issues a no - acknowledge in the 9 th clock cycle and a start in the 10 th . 3. the bus master issues a stop in the 9 th clock cycle. bus contention may result. 4. the bus master issues a start in the 9 th clock cy cle. bus contention may result. if the internal address reaches 1ffh it will wrap around to 000h on the next read cycle. figures 7 and 8 below show the proper operation for current address reads. selective (random) read a simple technique allows a user to select a random address location as the starting point for a read operation. this involves using the first two bytes of a write operation to set the internal address byte followed by subsequent read operations. to perform a selective read, the bus maste r sends out the slave address with the lsb set to 0. this specifies a write operation. according to the write protocol, the bus master then sends the word address byte that is loaded into the internal address latch. after the FM24C04 acknowledges the word address, the bus master issues a start condition. this simultaneously aborts the write operation and allows the read command to be issued with the slave address lsb set to a 1. the operation is now a current address read. this operation is illustrated in f igure 9.
ramtron FM24C04 28 july 2000 7 / 13 figure 7 current address read s s l a v e a d d r e s s 1 b y m a s t e r b y f m 2 4 c 0 4 s t a r t s t o p a a c k n o w l e d g e d a t a b y t e 1 p a d d r e s s d a t a n o a c k n o w l e d g e figure 8 sequential read s s l a v e a d d r e s s 1 b y m a s t e r b y f m 2 4 c 0 4 s t a r t s t o p a a c k n o w l e d g e d a t a b y t e 1 p a d d r e s s n o a c k n o w l e d g e d a t a b y t e d a t a a a a c k n o w l e d g e figure 9 selective (random) read s s l a v e a d d r e s s 1 b y m a s t e r b y f m 2 4 c 0 4 s t a r t s t o p a d a t a b y t e 1 p a d d r e s s n o a c k n o w l e d g e a s s l a v e a d d r e s s 0 s t a r t a a c k n o w l e d g e a d d r e s s w o r d a d d r e s s a d a t a a c k n o w l e d g e data retention and endurance data retention is specified in the electrical specifications belo w. for purposes of clarity, this section contrasts the retention and endurance of fram with eeprom. the retention performance of fram is very comparable to eeprom in its characteristics. however, the effect of endurance cycles on retention is different. a typical eeprom has a write endurance specification that is fixed. surpassing the specified level of cycles on an eeprom usually leads to a hard memory failure. by contrast, the effect of increasing cycles on fram produces an increase in the soft error r ate. that is, there is a higher likelihood of data loss but the memory continues to function properly. a hard failure would not occur by simply exceeding the endurance specification; simply a reduction in data retention reliability. while enough cycles wou ld cause an apparent hard error, this is simply a very high soft error rate. this characteristic makes it problematic to assign a fixed endurance specification. endurance is a soft specification. therefore, the user may operate the device with different levels of endurance cycling for different portions of the memory. for example, critical data needing the highest reliability level could be stored in memory locations that receive comparatively few cycles. data with shorter - term use could be located in an area receiving many more cycles. a scratchpad area, needing little if any retention can be cycled until there is virtually no retention capability remaining. this would occur several orders of magnitude above the endurance spec. internally, a fram operat es with a read and restore mechanism similar to a dram. therefore, endurance cycles are applied for each access: read or write. the fram architecture is based on an array of rows and columns. each access causes a cycle for an entire row. therefore, data lo cations targeted for substantially differing numbers of cycles should not be located within the same row. in the FM24C04, there are 64 rows each 64 bits wide. each 8 bytes in the address mark the beginning of a new row.
ramtron FM24C04 28 july 2000 8 / 13 applications the versatility of fra m technology fits into many diverse applications. clearly the strength of higher write endurance and faster writes make fram superior to eeprom in all but one - time programmable applications. the advantage is most obvious in data collection environments whe re writes are frequent and data must be nonvolatile. the attributes of fast writes and high write endurance combine in many innovative ways. a short list of ideas is provided here. 1. data collection . in applications where data is collected and saved, fram provides a superior alternative to other solutions. it is more cost effective than battery backup for sram and provides better write attributes than eeprom. 2. configuration . any nonvolatile memory can retain a configuration. however if the configuration c hanges and power failure is a possibility, the higher write endurance of fram allows changes to be recorded without restriction. any time the system state is altered, the change can be written. this avoids writing to memory on power down when the available time is short and power scarce. 3. high noise environments . writing to eeprom in a noisy environment can be challenging. when severe noise or power fluctuations are present, the long write time of eeprom creates a window of vulnerability during which the wr ite can be corrupted. the fast write of fram is completed within a microsecond. this time is typically too short for noise or power fluctuation to disturb it. 4. time to market . in a complex system, multiple software routines may need to access the nonvolati le memory. in this environment the time delay associated with programming eeprom adds undue complexity to the software development. each software routine must wait for complete programming before allowing access to the next routine. when time to market is critical, fram can eliminate this simple obstacle. as soon as a write is issued to the FM24C04, it is effectively done -- no waiting. 5. rf/id . in the area of contactless memory, fram provides an ideal solution. since rf/id memory is powered by an rf field, the long programming time and high current consumption needed to write eeprom is unattractive. fram provides a superior solution. the FM24C04 is suitable for multi - chip rf/id products. 6. maintenance tracking . in sophisticated systems, the operating history and system state during a failure is important knowledge. maintenance can be expedited when this information has been recorded. due to the high write endurance, fram makes an ideal system log. in addition, the convenient 2 - wire interface of the FM24C04 all ows memory to be distributed throughout the system using minimal additional resources.
ramtron FM24C04 28 july 2000 9 / 13 electrical specifications absolute maximum ratings description ratings ambient storage or operating temperature - 40 c to + 85 c voltage on any pin with res pect to ground - 1.0v to +7.0v d.c. output current on any pin 5 ma lead temperature (soldering, 10 seconds) 300 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and t he functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliability d c operating conditions ta = - 40 c to + 85 c, vdd = 4.5v to 5.5v unless otherwise specified symbol parameter min typ max units notes vdd main power supply 4.5 5.0 5.5 v 1 i dd vdd supply current @ scl = 100 khz 115 150 m a 2 i dd vdd supply current @ scl = 400 khz 400 500 m a 2 isb standby current 1 10 m a 3 ili input leakage current 10 m a 4 ilo output leakage current 10 m a 4 vil input low voltage - 0.3 vdd x 0.3 v 1 vih input high voltage vdd x 0.7 vdd + 0.5 v 1 vol output low voltage @ iol = 3 ma 0.4 v 1 vol output low voltage @ iol = 6 ma 0.6 v 1,5 vhys input hysteresis vdd x .05 v 1, 5 notes 1. referenced to vss. 2. scl toggling between vdd - 0.3v and vss, other inputs vss or vdd - 0.3v 3. scl = sda = vdd. all inputs vss or vdd. stop c ommand issued. 4. vin or vout = vss to vdd 5. this parameter is periodically sampled and not 100% tested.
ramtron FM24C04 28 july 2000 10 / 13 ac parameters ta = - 40 c to + 85 c, vdd = 4.5v to 5.5v unless otherwise specified symbol parameter standard mode fast mode units notes min max min m ax fscl scl clock frequency 0 100 0 400 khz tsp noise suppression time constant on scl, sda 50 50 ns taa scl low to sda data out valid 3 0.9 m s tbuf bus free before new transmission 4.7 1.3 m s thd:sta start condition hold time 4.0 0.6 m s tlow clock low period 4.7 1.3 m s thigh clock high period 4.0 0.6 m s tsu:sta start condition setup for repeated start 4.7 0.6 m s thd:dat data in hold 0 0 n s tsu:dat data in setup 250 100 n s trise sda and scl rise time 1000 20 + 0.1 cb 300 n s 1,2 tfall sda and scl fall time 300 20 + 0.1 cb 300 n s 1,2 tsu:sto stop condition setup 4.0 0.6 m s tdh data output hold (from scl @ vil) 0 0 ns tof output fall time (vih min to vil max) 250 20 + 0.1 cb 250 ns 1,2 notes : all scl sp ecifications as well as start and stop conditions apply to both read and write operations. 1 this parameter is periodically sampled and not 100% tested. 2 cb = total capacitance of one bus line in pf. capacitance ta = 25 c , f=1.0 mhz, vdd = 5v symbol p arameter max units notes ci/o input/output capacitance (sda) 8 pf 1 cin input capacitance 6 pf 1 notes 1 this parameter is periodically sampled and not 100% tested. ac test conditions input pulse levels vdd * 0.1 to vdd * 0.9 input rise and fall times 10 ns input and output timing levels vdd*0.5 equivalent ac load circuit
ramtron FM24C04 28 july 2000 11 / 13 diagram notes all start and stop timing parameters apply to both read and write cycles. clock specifications are identical for read and write cycles. write ti ming parameters apply to slave address, word address, and write data bits. functional relationships are illustrated in the relevant data sheet sections. these diagrams illustrate the timing parameters only. read bus timing write bus tim ing data retention ta = - 40 c to + 85 c, vdd = 4.5v to 5.5v unless otherwise specified parameter min units notes data retention 10 years 1 notes 1. data retention is specified at 85 c. the relationship between retention, temperature , and the associated reliability level is characterized separately.
ramtron FM24C04 28 july 2000 12 / 13 8 - pin sop (jedec) controlling dimensions is in millimeters. conversions to inches are not exact. symbol dim min nom. max a mm in. 1.35 .053 1.75 .069 a1 mm in. .10 .004 .25 .010 b mm in. .33 .013 .51 .020 c mm in. .19 .007 .25 .010 d mm i n. 4.80 .189 5.00 .197 e mm in. 3.80 .150 4.00 .157 e mm in. 1.27 bsc .050 bsc h mm in. 5.80 .228 6.20 .244 h mm in. .25 .010 .50 .197 l mm in. .40 .016 1.27 .050 a 0 8
ramtron FM24C04 28 july 2000 13 / 13 8 - pin dip (jedec) controlling dimensions is in inches. conversions to millimeters are not exact. symbol dim min nom. max a in. mm .210 5.33 a1 in. mm 0.015 .381 a2 in. mm 0.115 2.92 0.130 3.30 0.195 4.95 b in. mm 0.014 .356 0.018 .457 0.022 .508 d in. mm 0.355 9.02 0.365 9.27 0.400 10.2 d1 in. mm 0.005 .127 e in. mm 0.300 7.6 2 0.310 7.87 0.325 8.26 e1 in. mm 0.240 6.10 0.250 6.35 0.280 7.11 e in. mm .100 bsc 2.54 bsc ea in. mm .300 bsc 7.62 bsc eb in. mm 0.430 10.92 l in. mm 0.115 2.92 0.130 3.30 0.150 3.81

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